High Rate and Low Damage Etching Method as Pre Treatment of Seed Layer Sputtering for Fan out Panel Level Packaging

Abstract

This paper reports advanced pre treatment method before seed layer sputtering for Fan Out Panel Level Packaging (FOPLP). To realize high performance semiconductor devices, not only miniaturization of semiconductor chip but also minimizing packaging wiring length is also important. Fan out technology can take more I/O numbers than Fan In technology, so it is one of solution for short distance wiring, low power consumption and high density packaging. This technology originally started with wafer level process, but now its technology is going to spread to larger substrate like over 600mm square[1][2]. Enlarging substrate size is good way to suppress cost of ownership of manufacturing semiconductor devices. FOPLP is a kind of collaboration with front end technology which has fine pitch line and space and back end technology of packaging to realize high density and low cost semiconductor devices. In this technology, seed layer formation for re-distribution layer (RDL) is important to product fine pitch line and space wiring. Dielectric layer between top and bottom wiring is mainly polyimide called photosensitive imageable dielectric (PID) which can make pattern without photoresist. And to form good seed layer on polyimide with sputtering, pre treatment of polyimide is critical. We modified pre treatment for seed layer with sputtering in terms of productivity, adhesion and contact resistance.