{"title":"Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems","authors":"Tae-Hwan Kim, I. Park","doi":"10.1109/SIPS.2007.4387543","DOIUrl":null,"url":null,"abstract":"Targeting IEEE 802.16d systems, this paper presents a new approach for coarse time synchronization and carrier frequency offset estimation. In contrast to the previous architecture that usually computes both of them jointly within a unified auto-correlator, the proposed one performs them separately to achieve more reliable frequency synchronization and to reduce the overall hardware complexity by optimizing them individually. Experimental results show that the proposed architecture leads to better frequency synchronization compared to the previous joint estimation, and is more efficient in both respects of silicon area and power consumption.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"110 1","pages":"193-198"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2007.4387543","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
Targeting IEEE 802.16d systems, this paper presents a new approach for coarse time synchronization and carrier frequency offset estimation. In contrast to the previous architecture that usually computes both of them jointly within a unified auto-correlator, the proposed one performs them separately to achieve more reliable frequency synchronization and to reduce the overall hardware complexity by optimizing them individually. Experimental results show that the proposed architecture leads to better frequency synchronization compared to the previous joint estimation, and is more efficient in both respects of silicon area and power consumption.