Variation-aware study of BJT-based capacitorless DRAM cell scaling limit

Abstract

The scaling limit of the BJT-based capacitorless DRAM cell is investigated via 3-D process and device simulations, accounting for systematic and random sources of variation. The cell design and operating voltages are optimized at each gate length, following a constant electric field methodology. Retention time decreases with gate length, so that the scaling limit is expected to be 16.5 nm or 13 nm, depending on the application.