Unintentional Islanding Evaluation Utilizing Discrete RLC Circuit Versus Power Hardware-in-the Loop Method

Abstract

The high penetration of photovoltaic (PV) distributed energy resources (DER) facilitates the need for today’s systems to provide grid support functions and ride-through voltage and frequency events to minimize the adverse impacts on the distribution power system. These new capabilities and its requirements have created concerns that autonomous unintentional islanding (UI) algorithms are not sufficient to prevent a condition were the loss of utility is detected. Type tests in IEEE 1547-2018 have evolved to thoroughly evaluate DER capabilities and a new method includes power hardware-in-the-loop (PHIL) testing. Sandia National Laboratories is performing a detailed laboratory comparison of the tuned Resistive, Inductive, Capacitive (RLC) circuit method using discrete elements and the PHIL that applies the PV inverter equipment under test (EUT), real-time simulator, and a power amplifier. The PHIL method allows UI assessments without the need for potentially expensive, large, heat generating discrete loads.