A design-space exploration tool for low-power DCT and IDCT hardware accelerators

Abstract

The discrete cosine transform (DCT) and its inverse (IDCT) are often used for image compression and decompression. Truncated-matrix multipliers offer reduced area, power and delay at the expense of increased computational error. This paper describes a software tool for design-space exploration of low-power DCT and IDCT hardware accelerators that use truncated-matrix multipliers. The tool has an interactive graphical user interface and is written entirely in Java. It can open image files, simulate compression and/or decompression, and display the processed image and error statistics.