Design of low power CMOS drivers based on charge recycling

Abstract

The design of low power CMOS drivers using a charge recycling technique is introduced in this paper. Assuming simultaneous change of complementary signals, the half of the charge stored in the load capacitances is reused in every signal transition. All the control signals are generated by using completely digital logic and conventional technology. Compared to traditional taper buffers, power savings over 45% are obtained for the output load transitions. No speed degradation is observed but almost duplication of the silicon area is required.