J. Lau, C. Ko, C. Peng, Kai-Ming Yang, Tim Xia, P. Lin, Jean-Jou Chen, Po-Chun Huang, Tzvy-Jang Tseng, E. Lin, Leo Chang, Curry Lin, Winnie Lu
{"title":"Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration","authors":"J. Lau, C. Ko, C. Peng, Kai-Ming Yang, Tim Xia, P. Lin, Jean-Jou Chen, Po-Chun Huang, Tzvy-Jang Tseng, E. Lin, Leo Chang, Curry Lin, Winnie Lu","doi":"10.4071/imaps.1137828","DOIUrl":null,"url":null,"abstract":"\n In this investigation, the chip-last, RDL (redistribution-layer)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a FOPLP method on a 20mm × 20mm RDL-first substrate fabricated on a 515mm × 510mm temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a PCB (printed circuit board) is performed and test results including failure analysis are presented. Some recommendations are also provided.","PeriodicalId":14363,"journal":{"name":"International Symposium on Microelectronics","volume":"49 1","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Microelectronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4071/imaps.1137828","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this investigation, the chip-last, RDL (redistribution-layer)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a FOPLP method on a 20mm × 20mm RDL-first substrate fabricated on a 515mm × 510mm temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a PCB (printed circuit board) is performed and test results including failure analysis are presented. Some recommendations are also provided.
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