A Location Analysis for Dynamic Verification

Abstract

Dynamic verification is used extensively in making sure the logical correctness of design. Coverage is often used to measure the progress of the current verification. After the coverage criteria has been met, there may still be potential bugs that have not been detected. This paper proposes a method to help engineers analyze where the potential bug is most likely to occur. We construct a cover framework and propose an algorithm to calculate the probability. Experimental results based on Monte Carlo simulation are agreed with our algorithm.