{"title":"Examination of design and manufacturing issues in a 10 nm double gate MOSFET using nonequilibrium Green's function simulation","authors":"Z. Ren, R. Venugopal, S. Datta, M. Lundstrom","doi":"10.1109/IEDM.2001.979435","DOIUrl":null,"url":null,"abstract":"The double gate (DG) MOSFET and similar structures provide the electrostatic integrity needed to scale devices to their limits. In this paper, we use a non-equilibrium Green's function (NEGF) approach to examine 10 nm-scale device design and manufacturing issues realistically. NEGF simulations are used to examine: (i) choice of body thickness, (ii) effect of body thickness variations, (iii) the required junction abruptness, (iv) sensitivity of the device to gate-S/D (source/drain) over/underlap, and (v) the impact of metal-semiconductor contact resistance. The results of this study identify key device challenges for 10 nm-scale MOSFETs.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"30 9 1","pages":"5.4.1-5.4.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979435","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 43
Abstract
The double gate (DG) MOSFET and similar structures provide the electrostatic integrity needed to scale devices to their limits. In this paper, we use a non-equilibrium Green's function (NEGF) approach to examine 10 nm-scale device design and manufacturing issues realistically. NEGF simulations are used to examine: (i) choice of body thickness, (ii) effect of body thickness variations, (iii) the required junction abruptness, (iv) sensitivity of the device to gate-S/D (source/drain) over/underlap, and (v) the impact of metal-semiconductor contact resistance. The results of this study identify key device challenges for 10 nm-scale MOSFETs.