A full E-beam 0.25 mu m bipolar technology with sub-25 ps ECL gate delay

International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI:10.1109/IEDM.1991.235267

J. Warnock, J. Cressler, P. Coane, K. Chiong, M. Rothwell, K. Jenkins, J. Burghartz, E. Petrillo, N. Mazzeo, A. Megdanis, F. Hohn, M. Thomson, J. Sun, D. Tang

引用次数: 4

Abstract

Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA.<>

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全电子束0.25 μ m双极技术，ECL栅极延迟低于25 ps

只提供摘要形式。电子束光刻所提供的充分杠杆作用已在0.25 μ m双极工艺中得到充分利用。紧密的覆盖能力在缩小晶体管的整体尺寸方面提供了显著的优势。结合优化的器件技术，提供33 ghz 0.25 μ m发射极器件，最终实现了24 ps的ECL(发射极耦合逻辑)延迟，开关电流仅为1.1 mA。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

International Electron Devices Meeting 1991 [Technical Digest]

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