Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology

Abstract

A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.