Controlling Die Warpage by Applying Under Bump Metallurgy for Fan-Out Package Process Applications

Abstract

We investigated die warpage by applying under bump metallurgy (UBM) on die backside metallization for fan-out package process applications. An oxidized silicon wafer was used for the substrate, and an oxide layer was used on the active side of the die. Die warpage was controlled by applying UBM layers on the die backside. The thickness of the copper in the UBM layers was varied to 3 µm, 5 µm, and 7 µm. Two types of polyimide (PI) layers between the UBM layers formed and reduced die warpage, which was measured by the shadow moiré measurement method. Also, the thickness of the electro-plated copper in the UBM layers and the PI layers before the UBM layers affected the degree of die warpage during reflow. When forming the PI layer on the die before the UBM, the degree of die warpage was decreased compared to that without the PI layer in the cooling temperature range of the reflow profile. The silicon dies exhibited no warpage near the solder solidification temperature. This structure and process using a backside UBM layer and molten solder in the flip-chip bonding not only improved die shifts, but controlled die warpage during die pick -and-placement processes for fan-out packaging applications and also controlled die warpage during the die pick -and-placement step and in stack-via height formation process applications.