An ultra high speed architecture for VLSI implementation of hash functions

Abstract

Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. The research community efforts are also centered to the efficient implementation of them, in both software platforms and hardware devices. This work is related to hash functions FPGA implementation. Two different hash functions are studied: RIPEMD-160 and SHA-1. A high speed architecture is proposed for the implementation of both of them in the same hardware module. The proposed system reaches throughput values equal to 1,4 for SHA-1 and 1,6 for RIPEMND-160. The proposed system is compared with other related works in both software and hardware.