A Simplicial PWL Integrated Circuit Realization

M. D. Federico, P. Julián, Tomaso Poggi, M. Storace
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引用次数: 10

Abstract

In this paper we present a mixed-signal integrated circuit in a standard CMOS 0.5 µm technology implementing a piecewise-linear (PWL) function with three inputs, where each input can be either analog or coded with 8 bits. The output of the circuit is a digital word with 8-bit precision, representing the value of the PWL function at the three-dimensional input. The circuit accesses also a 4 kB external memory, which is addressed with a 12-bit word. Experimental results are shown that demonstrate the circuit working up to 50 MHz with a maximum power consumption of 3.7 mW.
一种简单的PWL集成电路实现
在本文中,我们提出了一个采用标准CMOS 0.5µm技术的混合信号集成电路,实现了具有三个输入的分段线性(PWL)功能,其中每个输入可以是模拟的,也可以是8位编码的。电路的输出是一个8位精度的数字字,表示三维输入处的PWL函数的值。该电路还访问一个4kb的外部存储器,该存储器用一个12位字进行寻址。实验结果表明,该电路工作频率高达50 MHz,最大功耗为3.7 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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2.00
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