Statistical variability study of a 10nm gate length SOI FinFET device

Abstract

A comprehensive statistical variability simulation study of a 10nm gate length FinFET device is presented. The FER-induced quantum confinement variation has a consistent impact on all device operation regions; while the RDD induced S/D resistance variation has little impact on the sub-threshold, but has relatively strong impact on the on-current, which is in contrast with the impact of GER on device characteristics. The statistical reliability simulation results indicate that the impact of NBTI/PBTI on individual device is the combined results of trap and fin configurations. Both statistical variability and reliability simulations demonstrate some degree of disentangling between sub-threshold and on-current behaviour. The advantage of FinFET technology is demonstrated by the result of statistical SRAM cell simulation.