Mixed analog-digital circuit for linear-time programmable sorting

G. Oddone, S. Rovetta, G. Uneddu, R. Zunino
{"title":"Mixed analog-digital circuit for linear-time programmable sorting","authors":"G. Oddone, S. Rovetta, G. Uneddu, R. Zunino","doi":"10.1109/ISCAS.1997.621538","DOIUrl":null,"url":null,"abstract":"The paper describes a VLSI circuit for sorting analog quantities. The circuit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"20 3","pages":"1968-1971 vol.3"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ISCAS.1997.621538","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"电路与系统学报","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ISCAS.1997.621538","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

The paper describes a VLSI circuit for sorting analog quantities. The circuit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.
用于线性时间可编程分选的混合模数电路
本文介绍了一种用于模拟量分选的VLSI电路。电路产生排序值的模拟表示,并对列表中相应的秩进行数字编码。排序列表的长度可以在运行时进行数字编程,因此也支持部分排序。模块化的混合模拟/数字结构被安排成在本地运行的基本单元。这大大方便了版面设计。电流模式和电压模式信号的适当耦合使晶体管的数量最小化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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