A worst case timing analysis technique for instruction prefetch buffers

Abstract

Predictable performance is crucial for real-time computing systems. We propose a buffered threaded prefetch scheme as a predictable and high performance instruction memory hierarchy. We also give extensions to the timing schema[3] to analyze the timing effects of the proposed scheme. In the extended timing schema, we associate with each program construct what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of the program construct. By defining a concatenation operation on WCTAs, our revised timing schema accurately accounts for the timing effects of the buffered threaded prefetching not only within but also across program constructs. This paper shows, through analysis using a timing tool based on the extended timing schema, the buffered prefetch scheme significantly improves the worst case execution times of tasks.