Design topologies with dual-Vth and dual-Tox assignment in 16 nm CMOS technology

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IET Computers and Digital Techniques Pub Date : 2020-04-30 DOI:10.1049/iet-cdt.2018.5211

Smita Singhal, Anu Mehra, Upendra Tripathi

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Abstract

This study presents different topologies for the assignment of dual threshold voltage and dual gate oxide thickness in 16 nm complementary metal-oxide-semiconductor technology. The objective is to optimise the circuit in terms of static power dissipation, delay, and power-delay-product (pdp). Topologies namely direct, grouping, and divide-by-2 are simulated for and conventional 1-bit full adder circuits. Results of the proposed topologies are compared with some of the existing techniques of leakage reduction i.e. dual-, dual- and supply switching with ground collapse (SSGC). 1-bit full adder circuit using direct topology reduces static power to 99.98, 96.71, and 95.86% as compared to static power in dual-, dual-, and SSGC techniques, respectively. The pdp of the circuit is significantly improved using proposed topologies. Thus, these topologies can be used for low power and high-performance applications with no area overhead.

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在16nm CMOS技术中设计具有双Vth和双Tox分配的拓扑结构

本研究提出了在16nm互补金属氧化物半导体技术中分配双阈值电压和双栅极氧化物厚度的不同拓扑结构。目标是在静态功耗、延迟和功率延迟乘积（pdp）方面优化电路。对于传统的1位全加电路，模拟了拓扑结构，即直接、分组和除以2。将所提出的拓扑结构的结果与一些现有的减少泄漏的技术进行了比较，即具有接地崩溃的双开关、双开关和电源开关（SSGC）。与双、双和SSGC技术中的静态功率相比，使用直接拓扑的1位全加电路将静态功率分别降低到99.98、96.71和95.86%。使用所提出的拓扑结构，电路的pdp得到了显著改进。因此，这些拓扑结构可以用于低功耗和高性能的应用，而不会产生区域开销。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.