VLSI implementation of anti-notch lattice structure for identification of exon regions in Eukaryotic genes

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Vikas Pathak, Satyasai Jagannath Nanda, Amit Mahesh Joshi, Sitanshu Sekhar Sahu
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引用次数: 6

Abstract

In a Eukaryotic gene, identification of exon regions is crucial for protein formation. The periodic-3 property of exon regions has been used for its identification. An anti-notch infinite impulse response (IIR) filter is mostly employed to recognise this periodic-3 property. The lattice structure realisation of anti-notch IIR filter requires less hardware over direct from-II structures. In this study, a hardware implementation of IIR anti-notch filter lattice structure is carried out on Zynq-series (Zybo board) field programmable gate array (FPGA). The performance of hardware design has been improved using techniques like retiming, pipelining and unfolding and finally assessed on various Eukaryotic genes. The hardware implementation reduces the time frame to analyse the DNA sequence of Eukaryotic genes for protein formation, which plays a significant role in detecting individual diseases from genetic reports. Here, the performance evaluation is carried out in MATLAB simulation environment and the results are found similar. Application-specific integrated circuit (ASIC) implementation of the anti-notch filter lattice structure is also carried out on CADENCE-RTL compiler. It is observed that the FPGA implementation is 31 to 34 times faster and ASIC implementation is 58 to 64 times faster compared to the results generated by MATLAB platform with similar prediction accuracy.

Abstract Image

用于真核基因外显子区域识别的反陷格结构的VLSI实现
在真核基因中,外显子区域的鉴定对蛋白质的形成至关重要。外显子区域的周期-3性质已用于其鉴定。抗陷波无限脉冲响应(IIR)滤波器主要用于识别这种周期-3性质。反陷波IIR滤波器的晶格结构实现需要比直接来自II结构更少的硬件。本研究在Zynq系列(Zybo板)现场可编程门阵列(FPGA)上实现了IIR抗陷波滤波器晶格结构的硬件实现。硬件设计的性能已经通过重新定时、流水线和展开等技术得到了改善,并最终在各种真核基因上进行了评估。硬件实现缩短了分析真核基因DNA序列以形成蛋白质的时间框架,这在从遗传报告中检测单个疾病方面发挥了重要作用。在此,在MATLAB仿真环境中进行了性能评估,结果相似。在CADENCE-RTL编译器上还实现了反陷波滤波器格结构的专用集成电路(ASIC)实现。与具有类似预测精度的MATLAB平台生成的结果相比,FPGA实现快31到34倍,ASIC实现快58到64倍。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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