LFSR-based generation of boundary-functional broadside tests

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IET Computers and Digital Techniques Pub Date : 2019-09-25 DOI:10.1049/iet-cdt.2019.0058

Irith Pomeranz

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引用次数: 1

Abstract

This study considers the compression of a type of close-to-functional broadside tests called boundary-functional broadside tests when the on-chip decompression logic consists of a linear-feedback shift register (LFSR). Boundary-functional broadside tests maintain functional operation conditions on a set of lines (called a boundary) in a circuit. This limits the deviations from functional operation conditions by ensuring that they do not propagate across the boundary. Functional vectors for the boundary are obtained from functional broadside tests. Seeds for the LFSR are generated directly from functional boundary vectors without generating tests or test cubes. Considering the tests that the LFSR produces, the seed generation procedure attempts to obtain the lowest possible Hamming distance between their boundary vectors and functional boundary vectors. It considers multiple LFSRs with increasing lengths to achieve test data compression. The procedure is structured to explore the trade-off between the level of test data compression and the Hamming distances or the proximity to functional operation conditions.

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基于LFSR的边界函数宽边测试生成

当片上解压缩逻辑由线性反馈移位寄存器（LFSR）组成时，本研究考虑了一种称为边界函数宽边测试的接近函数宽边的测试的压缩。边界函数宽边测试保持电路中一组线（称为边界）上的函数操作条件。这通过确保它们不会跨越边界传播来限制与功能操作条件的偏差。边界的函数向量是从函数宽边测试中获得的。LFSR的种子直接从函数边界向量生成，而不生成测试或测试立方体。考虑到LFSR产生的测试，种子生成过程试图获得它们的边界向量和函数边界向量之间尽可能低的汉明距离。它考虑了长度增加的多个LFSR，以实现测试数据压缩。该程序的结构旨在探索测试数据压缩水平与汉明距离或接近功能操作条件之间的权衡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.