Physical Parameter Variation Analysis on the Performance Characteristics of Nano DG-MOSFETs

Abstract

DG-MOSFETs are the most widely explored device architectures for na-no-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (t si < 10 nm) DG-MOS structures, charge carriers are affected by t si induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, I ON - I OFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (T op ), channel doping concentration (N c ), gate oxide thickness (t ox ) and Silicon film thickness (t si ). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLAS TM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.