Design Techniques for High-Speed Wireline Transmitters

Abstract

Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PAM4 prototype delivers an output swing of 630 mV $_{pp}$ with a clock jitter of 205 fs $_{rms}$ while drawing 44 mW.