Hybrid MTJ/CNTFET-Based Binary Synapse and Neuron for Process-in-Memory Architecture

Abstract

This letter develops a reliable, integrated binary synapse and neuron model for hardware implementation of binary neural networks. Thanks to the nonvolatile nature of magnetic tunnel junctions and the unique features of carbon nanotube field-effect transistors, the modeled design does not require external memory to store weights and also consumes low static power. Also, due to the circuit structure, which did not use sequential parts, the developed circuit is immune to soft error. Because, in binary neural networks, weights are limited to two values of −1 and 1, the occurrence of soft errors dramatically reduces the accuracy of the network. Simulation results indicate that the design in this work consumes at least 9% lower power, occupies 34% lower area, and offers a 49% lower power delay area product. Also, Monte Carlo simulations have been performed to study the effect of the process variation on the network. The result of the Monte Carlo simulations shows that the proposed neuron has no logical error in 10 000 simulations. Consequently, the accuracy of the network utilization by the neuron is equal to the software-implemented network and does not decrease even in the presence of process variations.