Performance Analysis of Bump in Tapered TSV: Impact on Crosstalk and Power Loss

Abstract

This study addresses the first feasible, and comprehensive approach to demonstrate a compact resistance-inductance-capacitance-conductance ( RLCG ) model for a multi-walled carbon nanotube bundle (MWB) and multilayered graphene nanoribbon (MLGNR) based tapered through silicon via ( T -TSV) along with the different shaped bumps. The physical structures of bumps accurately considered the effect of the high frequency resistive impact and the inter-metal dielectric (IMD) layer. A mathematical framework has been designed for the parasitics of the cylindrical, barrel, hourglass and the tapered bump structures. The bump and via parasitics have been computed by utilizing the current continuity expression, partial inductance method, splitting infinitesimally thin slices of bump and triangular arrangement of tube assemblage. In order to validate the proposed model, the EM simulation is performed and compared against the analytical results. A remarkable consistency of the analytical and EM simulation-based results supports the proposed model accuracy. Furthermore, when compared to the MWB based structures, the MLGNR -based tapered TSV shows a substantial improvement in power loss and crosstalk. Furthermore, regardless of via height, the TSV with tapered bump structure reduces the overall crosstalk induced delay by 33.22%, 28.90%, and 21.61%, respectively, when compared to the barrel, cylindrical and the hourglass structure.