{"title":"A Simplified Multilevel Space Vector Pulsewidth Modulation (SVPWM) Based on Boundary Lines, Including Overmodulation Zone","authors":"Amir Ostadrahimi;Stefano Bifaretti","doi":"10.1109/OJIA.2023.3289094","DOIUrl":null,"url":null,"abstract":"Space vector pulsewidth modulation (SVPWM) is a superior switching technique offering several benefits for power electronic inverters. However, concerning multilevel inverters (MLIs), implementing SVPWM is a demanding and time-consuming task because it deals with the six sectors of the space vector modulation (SVM) plane and numerous regions and vectors. Several research works in the literature tried to simplify SVPWM implementation for MLIs. This article introduces an SVPWM strategy, aiming to simplify the designing process and reduce the computational burden of the multilevel SVPWM. In this method, the switching process is designed only for the first sector of the SVM plane. The duty cycles and the switching states of the other sectors are assigned by transferring and translating techniques. The proposed method only uses basic algebraic functions in order to save the limited hardware resources of the processor. The same basic functions are used to handle overmodulation operations. This method introduces the boundary lines concept, which is a useful tool to detect the region and assign the switching states. Simulation and hardware-in-the-loop results are provided to validate the functionality of the proposed SVPWM. The hardware resource used on the field-programmable gate array module is adopted as a criterion to compare the proposed method with one of the conventional SVPWMs. This article is accompanied by MATLAB simulation files, for a three-level and a five-level inverter, provided by the authors as supplementary material.","PeriodicalId":100629,"journal":{"name":"IEEE Open Journal of Industry Applications","volume":"4 ","pages":"215-226"},"PeriodicalIF":7.9000,"publicationDate":"2023-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782707/10008994/10164229.pdf","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of Industry Applications","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10164229/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Space vector pulsewidth modulation (SVPWM) is a superior switching technique offering several benefits for power electronic inverters. However, concerning multilevel inverters (MLIs), implementing SVPWM is a demanding and time-consuming task because it deals with the six sectors of the space vector modulation (SVM) plane and numerous regions and vectors. Several research works in the literature tried to simplify SVPWM implementation for MLIs. This article introduces an SVPWM strategy, aiming to simplify the designing process and reduce the computational burden of the multilevel SVPWM. In this method, the switching process is designed only for the first sector of the SVM plane. The duty cycles and the switching states of the other sectors are assigned by transferring and translating techniques. The proposed method only uses basic algebraic functions in order to save the limited hardware resources of the processor. The same basic functions are used to handle overmodulation operations. This method introduces the boundary lines concept, which is a useful tool to detect the region and assign the switching states. Simulation and hardware-in-the-loop results are provided to validate the functionality of the proposed SVPWM. The hardware resource used on the field-programmable gate array module is adopted as a criterion to compare the proposed method with one of the conventional SVPWMs. This article is accompanied by MATLAB simulation files, for a three-level and a five-level inverter, provided by the authors as supplementary material.