By-Software Branch Prediction in Loops

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-08-11 DOI:10.1109/LCA.2023.3304613

Maziar Goudarzi;Reza Azimi;Julian Humecki;Faizaan Rehman;Richard Zhang;Chirag Sethi;Tanishq Bomman;Yuqi Yang

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引用次数: 0

Abstract

Load-Dependent Branches (LDB) often do not exhibit regular patterns in their local or global history and thus are inherently hard to predict correctly by conventional branch predictors. We propose a software-to-hardware branch pre-resolution mechanism that allows software to pass branch outcomes to the processor frontend ahead of fetching the branch instruction. A compiler pass identifies the instruction chain leading to the branch (the branch backslice ) and generates the pre-execute code that produces the branch outcomes ahead of the frontend observing them. The loop structure helps to unambiguously map the branch outcomes to their corresponding dynamic instances of the branch instruction. Our approach also allows for covering the loop iteration space selectively, with arbitrarily complex patterns. Our method for pre-execution enables important optimizations such as unrolling and vectorization, in order to substantially reduce the pre-execution overhead. Experimental results on select workloads from SPEC CPU 2017 and graph analytics workloads show up to 95% reduction of MPKI (21% on average), up to 39% speedup (7% on average), and 23% IPC gain on average, compared to a core with TAGE-SC-L-64KB branch predictor.

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循环中的软件分支预测

负载相关分支(Load-Dependent Branches, LDB)通常在其本地或全局历史中不显示规则模式，因此传统的分支预测器本质上难以正确预测。我们提出了一种软件到硬件的分支预解析机制，该机制允许软件在获取分支指令之前将分支结果传递给处理器前端。编译器通过识别通向分支的指令链(分支反片)，并生成预执行代码，这些代码在前端观察分支结果之前产生分支结果。循环结构有助于将分支结果明确地映射到分支指令的相应动态实例。我们的方法还允许有选择地覆盖循环迭代空间，使用任意复杂的模式。我们的预执行方法支持重要的优化，例如展开和向量化，以大大减少预执行开销。从SPEC CPU 2017和图形分析工作负载中选择工作负载的实验结果显示，与具有tag - sc - l - 64kb分支预测器的核心相比，MPKI降低了95%(平均21%)，加速提高了39%(平均7%)，IPC平均提高了23%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.