An Intermediate Language for General Sparse Format Customization

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jie Liu;Zhongyuan Zhao;Zijian Ding;Benjamin Brock;Hongbo Rong;Zhiru Zhang
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引用次数: 0

Abstract

The inevitable trend of hardware specialization drives an increasing use of custom data formats in processing sparse workloads, which are typically memory-bound. These formats facilitate the automated generation of target-aware data layouts to improve memory access latency and bandwidth utilization. However, existing sparse tensor programming models and compilers offer little or no support for productively customizing the sparse formats. Moreover, since these frameworks adopt an attribute-based approach for format abstraction, they cannot easily be extended to support general format customization. To overcome this deficiency, we propose UniSparse, an intermediate language that provides a unified abstraction for representing and customizing sparse formats. We also develop a compiler leveraging the MLIR infrastructure, which supports adaptive customization of formats. We demonstrate the efficacy of our approach through experiments running commonly-used sparse linear algebra operations with hybrid formats on multiple different hardware targets, including an Intel CPU, an NVIDIA GPU, and a simulated processing-in-memory (PIM) device.
通用稀疏格式自定义的中间语言
硬件专门化的必然趋势推动了在处理稀疏工作负载时越来越多地使用自定义数据格式,这些工作负载通常是内存受限的。这些格式有助于自动生成目标感知数据布局,从而改善内存访问延迟和带宽利用率。然而,现有的稀疏张量编程模型和编译器很少或根本不支持有效地定制稀疏格式。此外,由于这些框架采用基于属性的方法进行格式抽象,因此不容易对它们进行扩展以支持一般格式定制。为了克服这一缺陷,我们提出了UniSparse,这是一种中间语言,它为表示和定制稀疏格式提供了统一的抽象。我们还开发了一个利用MLIR基础设施的编译器,它支持自适应自定义格式。我们通过在多个不同的硬件目标(包括Intel CPU、NVIDIA GPU和模拟内存处理(PIM)设备)上以混合格式运行常用的稀疏线性代数操作的实验,证明了我们方法的有效性。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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