Gate Ringing in Superjunction MOSFETs with a Parasitic Capacitance in the Load Inductor

Abstract

In this paper, the origin of the gate oscillations with a stray capacitance in the load inductor is analyzed with a device/circuit mix-mode simulation. It is found that the gate ringing occurs when the superjunction device reaches its pinch-off potential (the n-pillar and the p-pillar are fully depleted by the lateral depletion process). The progress of the depletion profiles of the superjunction leads to a rapid change of the drain-to-source capacitance and the dV/dt. Finally, the dV/dt causes a sudden change of the current flow rate across the stray capacitance of the load inductor and the device while triggering the parasitic inductances. Based on these results, a comparative study was carried out with an ideal inductive load switching and, finally, the dampers for relieving the gate ringing were investigated.