In-Memory Versioning (IMV)

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-03-05 DOI:10.1109/LCA.2023.3273124

David Andrew Roberts;Haojie Ye;Tony Brewer;Sean Eilert

引用次数: 0

Abstract

In this letter, we propose and evaluate designs for a novel hardware-assisted data versioning system (in-memory versioning or IMV) in the context of high-performance computing. Our main novelty and advantage over recent published work is that it does not require any changes to host processor logic, instead augmenting a memory controller within memory modules. It is faster and more efficient than existing high-performance computing (HPC) checkpointing schemes and works from hours to sub-second checkpoint intervals. The main premise is to perform most operations in hardware at cache-line granularity, avoiding operating system (OS) latency and page copying bandwidth overhead. Energy is saved by keeping data movement in the memory module, compared with page granularity cross channel or cross-network copying that is currently used. For a 1-second checkpoint commit interval, we demonstrate up to 20x checkpoint performance and 70x energy savings using IMV versus page copy-on-write (COW).

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内存版本控制（IMV）

在这封信中，我们提出并评估了一种新的硬件辅助数据版本控制系统（内存版本控制或IMV）在高性能计算环境中的设计。与最近发表的工作相比，我们的主要新颖性和优势在于，它不需要对主机处理器逻辑进行任何更改，而是在内存模块中增强内存控制器。它比现有的高性能计算（HPC）检查点方案更快、更高效，工作时间从小时到亚秒不等。主要前提是在硬件中以缓存线粒度执行大多数操作，避免操作系统（OS）延迟和页面复制带宽开销。与当前使用的页面粒度跨通道或跨网络复制相比，通过在内存模块中保持数据移动可以节省能源。对于1秒的检查点提交间隔，我们使用IMV与写时页面复制（COW）相比，展示了高达20倍的检查点性能和70倍的节能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.