Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-03-16 DOI:10.1109/LCA.2023.3276709

Anurag Kar;Xueyang Liu;Yonghae Kim;Gururaj Saileshwar;Hyesoon Kim;Tushar Krishna

引用次数: 0

Abstract

Recent CPU microarchitectural attacks utilize contention over the NoC to mount covert and side-channel attacks on multicore CPUs and leak information from victim applications. We propose NoIR, a dynamic LLC slice selection mechanism using slice remapping to obfuscate interconnect contention patterns. NoIR reduces contention variance by 92.18% and mean IPC degradation due to cache invalidation is limited to 7.38% for SPEC CPU 2017 benchmarks for a 1000-access threshold. While previous defenses focused on redesigning the NoC and routing algorithms, we show that a top-down system-level approach can significantly raise the bar for a NoC security vulnerability with minimal modifications to the NoC hardware.

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利用LLC重映射缓解基于定时的NoC侧信道攻击

最近的CPU微体系结构攻击利用对NoC的争用对多核CPU发起隐蔽和侧通道攻击，并从受害应用程序泄漏信息。我们提出了NoIR，这是一种动态LLC片选择机制，使用片重映射来模糊互连争用模式。对于1000访问阈值的SPEC CPU 2017基准测试，NoIR将争用方差降低了92.18%，并且由于缓存无效导致的平均IPC降级限制在7.38%。虽然之前的防御侧重于重新设计NoC和路由算法，但我们表明，自上而下的系统级方法可以在对NoC硬件进行最小修改的情况下显著提高NoC安全漏洞的门槛。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.