SmartIndex: Learning to Index Caches to Improve Performance

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-04-05 DOI:10.1109/LCA.2023.3264478

Kevin Weston;Farabi Mahmud;Vahid Janfaza;Abdullah Muzahid

引用次数: 0

Abstract

Modern computers rely heavily on caches to achieve higher performance. Unfortunately, a cache indexing scheme can often cause an uneven distribution of addresses across cache sets resulting in many evictions of useful cache blocks. To address this issue, we propose SmartIndex , a self-optimized indexing scheme that leverages machine learning to actively learn the memory access pattern and dynamically adjust indexes to evenly distribute the cache lines across all sets in the cache, thereby reducing cache misses. Experimental results on a set of 26 memory-intensive applications show that for non-uniform applications, SmartIndex can reduce the misses per kilo instructions (MPKI) of a direct mapped cache by up to 39%, translating into an IPC speedup of 7.23% compared to the conventional power-of-two indexing scheme. Our experiments also show that SmartIndex can work with any cache associativity.

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SmartIndex:学习索引缓存以提高性能

现代计算机严重依赖缓存来实现更高的性能。不幸的是，缓存索引方案通常会导致地址在缓存集之间的不均匀分布，从而导致许多有用的缓存块被移除。为了解决这个问题，我们提出了SmartIndex，这是一种自优化的索引方案，它利用机器学习来主动学习内存访问模式，并动态调整索引，以将缓存线均匀分布在缓存中的所有集合中，从而减少缓存未命中。在一组26个内存密集型应用程序上的实验结果表明，对于非均匀应用程序，SmartIndex可以将直接映射缓存的每千指令未命中率（MPKI）降低39%，与传统的二次幂索引方案相比，IPC加速率为7.23%。我们的实验还表明，SmartIndex可以与任何缓存关联性一起工作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.