Six-Side Molded Panel-Level Chip Scale Package with Multiple Diced Wafers

Q4 Engineering

Journal of Microelectronics and Electronic Packaging Pub Date : 2020-09-01 DOI:10.4071/2380-4505-2020.1.000057

J. Lau, C. Ko, Tzvy-Jang Tseng, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, D. Cheng, Winnie Lu

{"title":"Six-Side Molded Panel-Level Chip Scale Package with Multiple Diced Wafers","authors":"J. Lau, C. Ko, Tzvy-Jang Tseng, C. Peng, Kai-Ming Yang, T. Xia, P. Lin, E. Lin, Leo Chang, H. Liu, Curry Lin, D. Cheng, Winnie Lu","doi":"10.4071/2380-4505-2020.1.000057","DOIUrl":null,"url":null,"abstract":"In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large temporary panel with multiple device wafers. Since all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Since all the processes/equipment are PCB process/equipment (not semiconductor process/equipment), it is a very low cost process. After the fabrication of RDLs, the wafers from the PCB panel are debonded. It is followed by solder ball mounting and fabricating the 6-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the 6-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"2020 1","pages":"000057-000066"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Microelectronics and Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.4071/2380-4505-2020.1.000057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}

引用次数: 2

Abstract

In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large temporary panel with multiple device wafers. Since all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Since all the processes/equipment are PCB process/equipment (not semiconductor process/equipment), it is a very low cost process. After the fabrication of RDLs, the wafers from the PCB panel are debonded. It is followed by solder ball mounting and fabricating the 6-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the 6-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.

查看原文本刊更多论文

六面模压面板级芯片规模封装与多片晶圆

在本研究中，介绍了六面模塑面板级芯片级封装（PLCSP）的设计、材料、工艺、组装和可靠性。重点是在具有多个器件晶片的大型临时面板上制造PLCSP的RDL（再分配层）。由于所有的印刷电路板（PCB）面板都是矩形的，一些器件晶片被切成两块或更多块，因此面板被充分利用。因此，它的吞吐量非常高。由于所有工艺/设备都是PCB工艺/设备（而不是半导体工艺/设备），因此这是一种成本非常低的工艺。在制造RDL之后，从PCB面板上剥离晶片。接下来是焊球安装，并用带有RDL的原始器件晶片制造6面成型的PLCSP。介绍了PLCSP的跌落试验和失效分析结果。通过非线性温度和时间相关有限元模拟，对6面成型PLCSP PCB组件进行了热循环。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Journal of Microelectronics and Electronic Packaging Engineering-Electrical and Electronic Engineering

CiteScore

1.30

自引率

0.00%

发文量

期刊介绍： The International Microelectronics And Packaging Society (IMAPS) is the largest society dedicated to the advancement and growth of microelectronics and electronics packaging technologies through professional education. The Society’s portfolio of technologies is disseminated through symposia, conferences, workshops, professional development courses and other efforts. IMAPS currently has more than 4,000 members in the United States and more than 4,000 international members around the world.