Analytical Multi-Parametric Design Optimization for the Miniaturization of Flip-Chip Package

Abstract

Recent advances in the microelectronics industry have increased the demand for smaller and more compact package devices with higher performance. This paper presents an analytical multi-parametric design optimization approach for the miniaturization of flip-chip package, while considering the filling time of the subsequent underfill encapsulation process. The design optimization approach was based on the latest regional segregation-based analytical filling time model. Numerical simulation was conducted to verify the governed analytical model. The discrepancies in filling times are less than 9.9% and the predicted critical bump pitch has a low deviation of 4.1%, affirming that both the analytical and numerical models were in great consensus. The variation effects of bump pitch, gap height and contact angle on the filling time were analysed and discussed thoroughly. Both the critical bump pitch and the critical gap height were computed and fitted into respective empirical equations. Subsequently, a new multi-parametric design optimization approach based on the thresholding and criticality of underfill parameters was proposed to determine the optimum parameters that yield to the most compact flip-chip package with acceptable low filling time during the encapsulation process. Lastly, this proposed optimization technique was tested on the four flip-chips used in a previously published underfill experiment.