Energy-Efficient Bayesian Inference Using Bitstream Computing

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-02-14 DOI:10.1109/LCA.2023.3238584

Soroosh Khoram;Kyle Daruwalla;Mikko Lipasti

引用次数: 0

Abstract

Uncertainty quantification is critical to many machine learning applications especially in mobile and edge computing tasks like self-driving cars, robots, and mobile devices. Bayesian Neural Networks can be used to provide these uncertainty quantifications but they come at extra computation costs. However, power and energy can be limited at the edge. In this work, we propose using stochastic bitstream computing substrates for deploying BNNs which can significantly reduce power and costs. We design our Bayesian Bitstream Processor hardware for an audio classification task as a test case and show that it can outperform a micro-controller baseline in energy by two orders of magnitude and delay by an order of magnitude, at lower power.

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基于比特流计算的节能贝叶斯推理

不确定性量化对许多机器学习应用至关重要，尤其是在自动驾驶汽车、机器人和移动设备等移动和边缘计算任务中。贝叶斯神经网络可以用来提供这些不确定性量化，但它们需要额外的计算成本。然而，功率和能量可能在边缘受到限制。在这项工作中，我们建议使用随机比特流计算基底来部署BNN，这可以显著降低功耗和成本。我们为音频分类任务设计了贝叶斯比特流处理器硬件作为测试用例，并表明在较低的功率下，它在能量和延迟方面可以优于微控制器基线两个数量级。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.