RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-03-13 DOI:10.1109/LCA.2023.3255555

Xia Zhao;Guangda Zhang;Lu Wang;Yangmei Li;Yongjun Zhang

引用次数: 0

Abstract

GPU chip module count is expected to keep increasing to meet the strong scaling demands of parallel applications. In many-chip-module GPUs, memory access latency seriously limits the performance since the transferring latency between different GPU modules is very high, which cannot be easily hidden by switching between different ready threads. To handle this problem, we propose RouteReplies, which enables a GPU module to fetch data from other GPU modules in the routing path. Leveraging the data locality between different GPU modules, RouteReplies significantly reduces the memory access latency since the memory request does not need to fetch data from the faraway memory partition. For a set of applications exhibiting varying degrees of inter-module locality, RouteReplies reduces memory access latency and increases performance by 54.8% on average (up to 364.8%).

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RouteReplies：缓解多芯片模块GPU的长延迟

GPU芯片模块数量预计将继续增加，以满足并行应用程序的强大扩展需求。在许多芯片模块GPU中，内存访问延迟严重限制了性能，因为不同GPU模块之间的传输延迟非常高，无法通过在不同的就绪线程之间切换来轻松隐藏。为了解决这个问题，我们提出了RouteReplies，它使GPU模块能够从路由路径中的其他GPU模块获取数据。利用不同GPU模块之间的数据局部性，RouteReplies显著降低了内存访问延迟，因为内存请求不需要从遥远的内存分区获取数据。对于一组表现出不同程度的模块间局部性的应用程序，RouteReplies可减少内存访问延迟，并将性能平均提高54.8%（最高可达364.8%）。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.