Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-03-12 DOI:10.1109/LCA.2023.3275909

Samer Kurzum;Gil Shomron;Freddy Gabbay;Uri Weiser

引用次数: 0

Abstract

Deep neural networks (DNNs) require abundant multiply-and-accumulate (MAC) operations. Thanks to DNNs’ ability to accommodate noise, some of the computational burden is commonly mitigated by quantization–that is, by using lower precision floating-point operations. Layer granularity is the preferred method, as it is easily mapped to commodity hardware. In this paper, we propose Dynamic Asymmetric Architecture (DAA), in which the micro-architecture decides what the precision of each MAC operation should be during runtime. We demonstrate a DAA with two data streams and a value-based controller that decides which data stream deserves the higher precision resource. We evaluate this mechanism in terms of accuracy on a number of convolutional neural networks (CNNs) and demonstrate its feasibility on top of a systolic array. Our experimental analysis shows that DAA potentially achieves 2x throughput improvement for ResNet-18 while saving 35% of the energy with less than 0.5% degradation in accuracy.

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通过动态不对称架构提高深度神经网络训练效率

深度神经网络(dnn)需要大量的乘法累加(MAC)运算。由于深度神经网络具有适应噪声的能力，一些计算负担通常可以通过量化来减轻，也就是说，通过使用精度较低的浮点运算。层粒度是首选的方法，因为它很容易映射到商用硬件。在本文中，我们提出了动态不对称架构(DAA)，其中微架构决定每个MAC操作在运行时的精度。我们演示了一个具有两个数据流和一个基于值的控制器的DAA，该控制器决定哪个数据流应该获得更高精度的资源。我们在许多卷积神经网络(cnn)上评估了这种机制的准确性，并证明了其在收缩阵列上的可行性。我们的实验分析表明，DAA有可能使ResNet-18的吞吐量提高2倍，同时节省35%的能量，精度下降不到0.5%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.