The Jaseci Programming Paradigm and Runtime Stack: Building Scale-Out Production Applications Easy and Fast

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-03-18 DOI:10.1109/LCA.2023.3274038

Jason Mars;Yiping Kang;Roland Daynauth;Baichuan Li;Ashish Mahendra;Krisztian Flautner;Lingjia Tang

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引用次数: 0

Abstract

Today's production scale-out applications include many sub-application components, such as storage backends, logging infrastructure and AI models. These components have drastically different characteristics, are required to work in collaboration, and interface with each other as microservices. This leads to increasingly high complexity in developing, optimizing, configuring, and deploying scale-out applications, raising the barrier to entry for most individuals and small teams. We developed a novel co-designed runtime system, Jaseci , and programming language, Jac , which aims to reduce this complexity. The key design principle throughout Jaseci's design is to raise the level of abstraction by moving as much of the scale-out data management, microservice componentization, and live update complexity into the runtime stack to be automated and optimized automatically. We use real-world AI applications to demonstrate Jaseci's benefit for application performance and developer productivity.

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Jaseci编程范式和运行时堆栈:构建横向扩展的生产应用程序容易和快速

今天的生产向外扩展应用程序包括许多子应用程序组件，例如存储后端、日志基础设施和AI模型。这些组件具有截然不同的特征，需要协同工作，并作为微服务相互连接。这导致开发、优化、配置和部署横向扩展应用程序的复杂性日益增加，提高了大多数个人和小型团队的进入门槛。我们开发了一种新的共同设计的运行时系统Jaseci和编程语言Jac，旨在降低这种复杂性。贯穿Jaseci设计的关键设计原则是通过将尽可能多的横向扩展数据管理、微服务组件化和实时更新复杂性转移到运行时堆栈中以实现自动化和自动优化，从而提高抽象级别。我们使用真实的AI应用程序来演示Jaseci对应用程序性能和开发人员生产力的好处。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.