LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-08-25 DOI:10.1109/LCA.2023.3287096

Yun-Chen Lo;Yu-Chih Tsai;Ren-Shuo Liu

引用次数: 0

Abstract

Computing latency is an important system metric for Deep Neural Networks (DNNs) accelerators. To reduce latency, this work proposes LV , a latency-versatile floating-point engine (FP-PE), which contains the following key contributions: 1) an approximate bit-versatile multiplier-and-accumulate (BV-MAC) unit with early shifter and 2) an on-demand fixed-point-to-floating-point conversion (FXP2FP) unit. The extensive experimental results show that LV outperforms baseline FP-PE and redundancy-aware FP-PE by up to 2.12× and 1.3× speedup using TSMC 40-nm technology, achieving comparable accuracy on the ImageNet classification tasks.

查看原文本刊更多论文

LV：用于高性能深度神经网络的潜伏通用浮点引擎

计算延迟是深度神经网络(dnn)加速器的重要系统指标。为了减少延迟，本工作提出了LV，一种延迟通用浮点引擎(FP-PE)，它包含以下关键贡献:1)具有早期移位器的近似位通用乘积(BV-MAC)单元和2)按需点到浮点转换(FXP2FP)单元。大量的实验结果表明，LV比使用台积电40纳米技术的基准FP-PE和冗余感知FP-PE的速度提高了2.12倍和1.3倍，在ImageNet分类任务上达到了相当的精度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.