Performance Analysis of 6T SRAM and ONOFIC Cells

Abstract

As the Technology node scales down to deep sub-micron regime, the design of static random-access memory (SRAM) cell becomes a critical issue because of increased leakage current components. These leakage current components prevent to design a low power processor as large of the processor power is consumed by the memory part. In this paper, a SRAM cell is designed based on ON/OFF logic (ONOFIC) approach. Static noise margin (SNM) of the cell for the different states are calculated and evaluated by using butterfly as well as noise (N) curves with the help of Cadence tools at 45 nm technology node. ONOFIC approach helps to reduce the leakage current components which makes a low power memory cell. A performance comparison is made between the conventional six-transistor (6T) SRAM cell and memory cell using ONOFIC approach. Low value of power delay product (PDP) is the outcome of ONOFIC approach as compared to conventional cell. ONOFIC approach decreases PDP by 99.99% in case of hold state. ONOFIC approach improves the different performance metrics for the different states of the SRAM cell.