ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA.

IF 1.6 4区计算机科学 Q3 COMPUTER SCIENCE, INFORMATION SYSTEMS

Journal of Signal Processing Systems for Signal Image and Video Technology Pub Date : 2019-01-01 Epub Date: 2019-01-02 DOI:10.1007/s11265-018-1424-1

Joost Hoozemans, Jeroen van Straten, Timo Viitanen, Aleksi Tervo, Jiri Kadlec, Zaid Al-Ars

{"title":"ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA.","authors":"Joost Hoozemans, Jeroen van Straten, Timo Viitanen, Aleksi Tervo, Jiri Kadlec, Zaid Al-Ars","doi":"10.1007/s11265-018-1424-1","DOIUrl":null,"url":null,"abstract":"The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.","PeriodicalId":50050,"journal":{"name":"Journal of Signal Processing Systems for Signal Image and Video Technology","volume":null,"pages":null},"PeriodicalIF":1.6000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1007/s11265-018-1424-1","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Signal Processing Systems for Signal Image and Video Technology","FirstCategoryId":"94","ListUrlMain":"https://doi.org/10.1007/s11265-018-1424-1","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2019/1/2 0:00:00","PubModel":"Epub","JCR":"Q3","JCRName":"COMPUTER SCIENCE, INFORMATION SYSTEMS","Score":null,"Total":0}

引用次数: 6

Abstract

The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.

Abstract Image

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ALMARVI执行平台:基于FPGA的异构视频处理SoC平台。

处理硬件替代品的激增允许开发人员使用各种定制的计算平台以最佳方式运行他们的应用程序。然而，在定制硬件上移植应用程序代码需要大量的开发和移植工作。本文描述了一个异构计算平台(ALMARVI执行平台)，该平台由多个通信处理器组成，可通过OpenCL接口轻松编程。ALMARVI平台使用基于VLIW和传输触发架构(分别为ρ-VEX和TCE核心)的处理元素。它可以在Zynq设备上实现，如ZedBoard，并通过pocl (Portable OpenCL)项目和我们的ALMAIF接口规范支持OpenCL。这允许开发人员透明地在任何一个处理元素上执行内核，从而允许以最小的设计和开发工作来优化执行时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Journal of Signal Processing Systems for Signal Image and Video Technology 工程技术-工程：电子与电气

CiteScore

4.00

自引率

0.00%

发文量

106

审稿时长

4-8 weeks

期刊介绍： The Journal of Signal Processing Systems for Signal, Image, and Video Technology publishes research papers on the design and implementation of signal processing systems, with or without VLSI circuits. The journal is published in twelve issues and is distributed to engineers, researchers, and educators in the general field of signal processing systems.