A Fully Implantable, Programmable and Multimodal Neuroprocessor for Wireless, Cortically Controlled Brain-Machine Interface Applications.

IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, INFORMATION SYSTEMS
Fei Zhang, Mehdi Aghagolzadeh, Karim Oweiss
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引用次数: 22

Abstract

Reliability, scalability and clinical viability are of utmost importance in the design of wireless Brain Machine Interface systems (BMIs). This paper reports on the design and implementation of a neuroprocessor for conditioning raw extracellular neural signals recorded through microelectrode arrays chronically implanted in the brain of awake behaving rats. The neuroprocessor design exploits a sparse representation of the neural signals to combat the limited wireless telemetry bandwidth. We demonstrate a multimodal processing capability (monitoring, compression, and spike sorting) inherent in the neuroprocessor to support a wide range of scenarios in real experimental conditions. A wireless transmission link with rate-dependent compression strategy is shown to preserve information fidelity in the neural data. At 32 channels, the neuroprocessor has been fully implemented on a 5mm×5mm nano-FPGA, and the prototyping resulted in 5.19 mW power consumption, bringing its performance within the power-size constraints for clinical use. The optimal design for compression and sorting performance was evaluated for multiple sampling frequencies, wavelet basis choice and power consumption.

一种完全可植入、可编程和多模态的神经处理器,用于无线、皮质控制的脑机接口应用。
可靠性、可扩展性和临床可行性是无线脑机接口系统(bmi)设计的关键。本文报道了一种神经处理器的设计和实现,用于调节通过长期植入清醒行为大鼠大脑的微电极阵列记录的原始细胞外神经信号。神经处理器的设计利用神经信号的稀疏表示来对抗有限的无线遥测带宽。我们展示了神经处理器固有的多模态处理能力(监测、压缩和尖峰排序),以支持实际实验条件下的广泛场景。提出了一种采用速率相关压缩策略的无线传输链路,以保持神经数据的信息保真度。在32通道时,神经处理器已经完全实现在5mm×5mm纳米fpga上,原型设计的功耗为5.19 mW,使其性能符合临床使用的功率尺寸限制。从多采样频率、小波基选择和功耗等方面对优化设计的压缩和排序性能进行了评价。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
4.00
自引率
0.00%
发文量
106
审稿时长
4-8 weeks
期刊介绍: The Journal of Signal Processing Systems for Signal, Image, and Video Technology publishes research papers on the design and implementation of signal processing systems, with or without VLSI circuits. The journal is published in twelve issues and is distributed to engineers, researchers, and educators in the general field of signal processing systems.
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