MRAM-Based CiM Architecture for Backpropagation-Free Training of Neural Networks Using DFA and DRTP

Abstract

Conventional backpropagation’s (BP) sequential nature limits its efficiency on compute-in-memory (CiM) architectures. To address this challenge, this work proposes the first CiM accelerator framework for training neural networks using direct feedback alignment (DFA) and direct random target propagation (DRTP) implemented on magnetoresistive random access memory (MRAM)-based CiM crossbars. By exploiting the inherent parallelism of these learning rules, the proposed design enables concurrent error propagation and weight-gradient computation for all layers. A CiM-aware mapping strategy is developed for forward computation, error projection, and gradient evaluation on crossbar arrays, along with hierarchical organization and pipelining to improve hardware utilization. The architecture is evaluated across fully connected and convolutional neural networks. Results show an average of 36% and 50% improvement in area and energy efficiency compared to BP-based training, while pipelining further reduces iteration latency and improves throughput. In particular, DRTP enables inter-iteration pipelining and achieves more than 100% higher throughput than BP in spin-orbit torque (SOT)-MRAM-based CiM architectures, demonstrating an efficient approach for scalable and energy-efficient on-chip neural network training.