A 340-GHz 7 × 2 Radiator Array With Coupled-Line-Based Mode-Decoupling Harmonic Enhancement and Chip-to-Waveguide Interface

Abstract

This article presents a 334–348-GHz $7\times 2$ radiator array that demonstrates enhanced power efficiency and high equivalent isotropically radiated power (EIRP). Each element operates at a fundamental frequency of approximately 170 GHz, with the second-order harmonic extracted to minimize harmonic conversion losses—a significant advancement over many existing solutions that rely on higher order harmonics. Furthermore, a coupled-line-based mode-decoupling harmonic enhancement (MDHE) technique is proposed to decouple the fundamental and harmonic modes, effectively boosting output power and suppressing signal leakage. To support system-level integration, a chip-to-waveguide interface is implemented, providing a standard waveguide port for the array’s radiated signal and enabling the use of off-chip components such as high-gain antennas. Fabricated using a 65-nm CMOS process, the radiator chip features a $7\times 2$ element array with on-chip loop antennas, all within a compact core area of 1.18 mm². It measures a 1-D beam-steering range of 80° and phase noise levels of –85.2 and –111.4 dBc/Hz at 1- and 10-MHz offsets from 340 GHz, respectively. Consuming 140 mW of DC power, the radiator delivers a radiated power of –4.2 dBm at 345.8 GHz, resulting in a DC-to-RF efficiency of 0.27%. This marks one of the highest reported efficiencies for CMOS radiators in the 330–500 GHz (Y-band) frequency range. Assembled with a transition waveguide horn and a Cassegrain antenna, the system achieves a peak EIRP of 30.5 dBm.