A CMOS Capacitive Fingerprint Sensor Chip with Column-Shared Charge-Accumulation Readout for Ridge-Valley Contrast Enhancement.

Abstract

Capacitive fingerprint sensors are widely used in mobile, access-control, IoT, and biometric authentication systems because of their compact size, low power consumption, low cost, and CMOS compatibility. However, the small capacitance difference between fingerprint ridges and valleys can be degraded by passivation thickness, skin condition, contact pressure, contamination, and circuit noise, especially in high-resolution sensors with reduced pixel pitch. This work presents a CMOS capacitive fingerprint sensor chip with a column-shared charge-accumulation readout to enhance ridge-valley contrast. The proposed readout repeatedly senses the same pixel and accumulates the resulting charge-domain signals at the column level before analog-to-digital conversion, improving ridge-valley separability without increasing pixel-level circuit complexity. The chip was fabricated in a 0.18 μm CMOS process and includes a 144 × 40 sensor array with a 50 μm pixel pitch, corresponding to approximately 508 dpi. Fingerprint images were acquired from two participants for accumulation numbers from N = 1 to N = 5. After image-quality screening, the average ridge-valley contrast increased from 5.71% to 43.86%, corresponding to a contrast ratio of approximately 7.68, while the average image-based ridge-valley SNR remained above 12 dB. The Energy-Contrast Efficiency (ECE) increased with N, although capture time and frame energy also increased. These results indicate that the proposed readout enhances ridge-valley contrast while the image-based ridge-valley SNR remains relatively stable.