Design and optimization of low-power approximate multipliers for error-tolerant image processing and CNN applications

Abstract

In error-tolerant applications such as image processing and neural network acceleration, the design of low-power architectures is critical. Approximate computing has emerged as an effective paradigm for developing energy-efficient arithmetic units by relaxing computational accuracy. This paper proposes a novel 4:2 approximate compressor architecture that complements exact compressors to form high-performance approximate multipliers. The proposed designs are synthesized using 90-nm CMOS technology in Cadence Genus and evaluated in terms of power, delay, and area. Simulation results demonstrate substantial improvements compared to existing state-of-the-art approximate multipliers. For 8-bit and 16-bit implementations, the proposed PM1, PHM, and PM2 multipliers achieve area reductions of 45%, 79%, and 18%, and 27%, 59%, and 13%, respectively. Power consumption is reduced by up to 31%, 77%, and 8% (10%, 51%, and 5% for 16-bit designs). Furthermore, the proposed architectures maintain acceptable image quality, exhibiting satisfactory peak signal-to-noise ratio (PSNR) values for image processing operations such as multiplication, smoothing, sharpening, and convolutional neural network (CNN) computations. These results confirm that the proposed approximate multipliers offer an effective trade-off between computational accuracy and hardware efficiency for error-tolerant image processing and CNN applications.