Novel Neural Network-Based Modeling Methodology and Performance Optimization for ESD Device

Abstract

Electrostatic discharge (ESD) constitutes a significant reliability issue in the manufacturing of advanced integrated circuits. However, the design and accurate simulation of on-chip ESD protection devices remain challenging due to the lack of standardized models and computer aided design tools that support comprehensive ESD device simulation. In this paper, we present a method for modeling the voltage-time (VT), current-time (IT), and quasi-static current-voltage (IV) curves of ESD protection devices using neural network models in machine learning. For method demonstration and experimental validation, resistor-capacitor-coupled low-voltage-triggered silicon-controlled rectifier and ESD N-well diodes were fabricated on 0.18 μm complementary metal-oxide-semiconductor (CMOS) and bipolar-CMOS-DMOS processes. The VT and IT curves obtained from 100 ns transmission line pulse testing were fitted and predicted, and the final quasi-static IV curves were calculated from the simulation results of these transient responses. Experimental results demonstrate that the simulation data achieve a coefficient of determination $(R^{2})$ greater than 0.99 against the measured data. Furthermore, the proposed modeling method is applicable to both primary categories of ESD protection devices (snapback and nonsnapback), offering a versatile technical approach for predicting the performance of ESD protection designs.