Back-Invalidate Timing: Coherence Channels in CXL 3.x Device-Coherent Memory

IF 2 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-09-29 DOI:10.1109/LCA.2026.3738639

Oğuz Ergin

引用次数: 0

Abstract

A cache line held exclusively by one core costs more to read than a shared one, and that difference carries a channel. CXL 3.x permits device-coherent memories on which that asymmetry reappears across a trust boundary, in two forms. A state channel follows from ordinary coherence resolution. An occupancy channel extends the specification’s own worked example, where a read stalls behind a back-invalidate snoop to an unrelated address until a snoop-filter entry can be allocated, so a requester reads pressure on a device-side structure without touching a line its peers touch. We name the assumptions each rests on, and the occupancy-channel construction runs between two hosts on an unmodified third-party model of a device-side filter, separating the two symbols with one error in 288 on a deterministic clock. The confidential-computing protocol declares the occupancy channel’s deployment in scope, then assumes away the resource it reads.

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反向无效时序：CXL 3中的相干通道。x Device-Coherent Memory

一个核心独占的高速缓存线比共享的高速缓存线读起来要花费更多的时间，而这一差异会带来一个通道。CXL 3。X允许设备一致的记忆，这种不对称在信任边界上以两种形式重现。状态通道遵循普通相干分辨率。占用通道扩展了规范自己的工作示例，在该示例中，在可以分配窥探过滤器条目之前，读取将在一个反向无效的窥探之后停留到一个不相关的地址，因此请求程序读取设备端结构上的压力，而不触及其对等程序所触及的线路。我们命名每个假设所依赖的假设，并且占用通道构造在未修改的第三方设备端过滤器模型上的两台主机之间运行，在确定性时钟上分离两个符号，在288中有一个错误。保密计算协议声明占用通道在作用域中的部署，然后假定它读取的资源消失。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.