A Twin-FeFET MLC CIM With Enhanced Voltage and Process Variation Tolerance for Edge Intelligence MAC and AP

Abstract

This paper introduces a voltage and process variation-tolerant non-volatile computing-in-memory (CIM) architecture based on the co-design of neural networks and circuit implementations. By exploiting the adjustable threshold voltage ( $V_{TH}$ ) of ferroelectric field-effect transistors (FeFETs), the proposed architecture features an active square-law compensation mechanism within a 2-FeFET-1-Transistor-1-Capacitor (2F-1T-1C) single cell (S-Cell) to perform highly linear multiply-accumulate (MAC) computations. To further enable high-precision operations and global average pooling (AP), we propose a twin-cell (T-Cell) extension (FeMAPIM). The T-Cell leverages an asymmetric capacitive ratio (4:1) that not only drastically reduces the average per-cell capacitor area overhead but also acts as a spatial filter for variations. The architecture is comprehensively evaluated across cell and array levels. System-level assessments on VGG-GAP, ResNet-20, and MobileNetV2 using CIFAR datasets confirm that the proposed macro tightly suppresses hardware-induced accuracy degradation, delivering highly robust inference for edge intelligence.