Efficient memory element design based on ferroelectric carbon nanotube transistors

Abstract

As technology advances and transistor dimensions decrease, physical limitations and performance challenges have slowed down the miniaturization of CMOS-based circuits. In such a situation, continued development requires the use of alternative technologies instead of simply reducing dimensions. In this regard, carbon nanotube field-effect transistors (CNTFETs) have been proposed as promising options due to their favorable electronic properties, as well as the use of ferroelectric materials in the gate stack to exploit the negative capacitance property. On the other hand, the limitations of binary logic in the efficient implementation of some applications have increased attention to multi-level logic, especially three-level logic. In this study, a compact three-level memory cell based on CNTFET is presented using the negative capacitance (NC) property of ferroelectric materials integrated into the gate stack. Unlike conventional FeFETs that primarily exploit remanent polarization states for non-volatile storage, the proposed NC-CNTFET utilizes the negative-capacitance effect to modify the gate electrostatics and provide internal voltage amplification. In contrast to conventional logic-oriented NC-FETs, where ferroelectric hysteresis is generally minimized, the polarization hysteresis is intentionally retained in the proposed memory operating regime and utilized together with the negative differential resistance (NDR) characteristic to establish a zero-gain region in the voltage transfer characteristic (VTC), thereby enabling three distinct stable logic states. The memory structure consists of two coupled inverters and pass-type access transistors, and has a good static noise margin (SNM) without the need to add an additional transistor, due to the hysteresis property of ferroelectric materials. The results show that the proposed design has reduced the read delay and significantly improved the read energy (up to 84%) compared to previous works, although it is accompanied by a relative increase in the delay and write energy.