{"title":"FlexNM: A Fully Flexible SpMM Accelerator for N:M Structured Sparsity","authors":"Jaehun Han;Wan Choi","doi":"10.1109/LCA.2026.3735038","DOIUrl":null,"url":null,"abstract":"N:M structured pruning is widely adopted in modern transformer-based deep learning workloads to reduce model size and enable efficient Sparse-Dense Matrix Multiplication (SpMM). However, existing accelerators either support limited N:M configurations or require hardware regeneration for different sparsity patterns. This limitation prevents efficient acceleration under optimal sparsity patterns, forcing suboptimal N:M configurations or hardware redesign, and resulting in degraded model accuracy. To address this issue, we propose FlexNM, a fully flexible N:M structured SpMM accelerator. FlexNM employs a unified hardware architecture that supports a diverse range of N:M values, enabling direct acceleration of workloads at their optimal N:M sparsity configurations. To achieve this flexibility, FlexNM employs a novel asymmetric adder-tree (AAT) mapping scheme that efficiently supports diverse values of N. It also incorporates a bitmap-based compression scheme to reduce memory overhead and enhance N:M flexibility. FPGA experimental results show that FlexNM achieves up to a 15.94× speedup over the dense systolic-array baseline while requiring 1.47× LUT and 1.54× FF usage relative to the same baseline.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"391-394"},"PeriodicalIF":2.0000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Architecture Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11694208/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/9/16 0:00:00","PubModel":"Epub","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
N:M structured pruning is widely adopted in modern transformer-based deep learning workloads to reduce model size and enable efficient Sparse-Dense Matrix Multiplication (SpMM). However, existing accelerators either support limited N:M configurations or require hardware regeneration for different sparsity patterns. This limitation prevents efficient acceleration under optimal sparsity patterns, forcing suboptimal N:M configurations or hardware redesign, and resulting in degraded model accuracy. To address this issue, we propose FlexNM, a fully flexible N:M structured SpMM accelerator. FlexNM employs a unified hardware architecture that supports a diverse range of N:M values, enabling direct acceleration of workloads at their optimal N:M sparsity configurations. To achieve this flexibility, FlexNM employs a novel asymmetric adder-tree (AAT) mapping scheme that efficiently supports diverse values of N. It also incorporates a bitmap-based compression scheme to reduce memory overhead and enhance N:M flexibility. FPGA experimental results show that FlexNM achieves up to a 15.94× speedup over the dense systolic-array baseline while requiring 1.47× LUT and 1.54× FF usage relative to the same baseline.
期刊介绍:
IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.