FlexNM: A Fully Flexible SpMM Accelerator for N:M Structured Sparsity

IF 2 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
IEEE Computer Architecture Letters Pub Date : 2026-07-01 Epub Date: 2026-09-16 DOI:10.1109/LCA.2026.3735038
Jaehun Han;Wan Choi
{"title":"FlexNM: A Fully Flexible SpMM Accelerator for N:M Structured Sparsity","authors":"Jaehun Han;Wan Choi","doi":"10.1109/LCA.2026.3735038","DOIUrl":null,"url":null,"abstract":"N:M structured pruning is widely adopted in modern transformer-based deep learning workloads to reduce model size and enable efficient Sparse-Dense Matrix Multiplication (SpMM). However, existing accelerators either support limited N:M configurations or require hardware regeneration for different sparsity patterns. This limitation prevents efficient acceleration under optimal sparsity patterns, forcing suboptimal N:M configurations or hardware redesign, and resulting in degraded model accuracy. To address this issue, we propose FlexNM, a fully flexible N:M structured SpMM accelerator. FlexNM employs a unified hardware architecture that supports a diverse range of N:M values, enabling direct acceleration of workloads at their optimal N:M sparsity configurations. To achieve this flexibility, FlexNM employs a novel asymmetric adder-tree (AAT) mapping scheme that efficiently supports diverse values of N. It also incorporates a bitmap-based compression scheme to reduce memory overhead and enhance N:M flexibility. FPGA experimental results show that FlexNM achieves up to a 15.94× speedup over the dense systolic-array baseline while requiring 1.47× LUT and 1.54× FF usage relative to the same baseline.","PeriodicalId":51248,"journal":{"name":"IEEE Computer Architecture Letters","volume":"25 2","pages":"391-394"},"PeriodicalIF":2.0000,"publicationDate":"2026-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Architecture Letters","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/11694208/","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"2026/9/16 0:00:00","PubModel":"Epub","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

N:M structured pruning is widely adopted in modern transformer-based deep learning workloads to reduce model size and enable efficient Sparse-Dense Matrix Multiplication (SpMM). However, existing accelerators either support limited N:M configurations or require hardware regeneration for different sparsity patterns. This limitation prevents efficient acceleration under optimal sparsity patterns, forcing suboptimal N:M configurations or hardware redesign, and resulting in degraded model accuracy. To address this issue, we propose FlexNM, a fully flexible N:M structured SpMM accelerator. FlexNM employs a unified hardware architecture that supports a diverse range of N:M values, enabling direct acceleration of workloads at their optimal N:M sparsity configurations. To achieve this flexibility, FlexNM employs a novel asymmetric adder-tree (AAT) mapping scheme that efficiently supports diverse values of N. It also incorporates a bitmap-based compression scheme to reduce memory overhead and enhance N:M flexibility. FPGA experimental results show that FlexNM achieves up to a 15.94× speedup over the dense systolic-array baseline while requiring 1.47× LUT and 1.54× FF usage relative to the same baseline.
FlexNM: N:M结构稀疏的全柔性SpMM加速器
N:M结构化剪枝在现代基于变压器的深度学习工作负载中被广泛采用,以减小模型大小并实现高效的稀疏密集矩阵乘法(SpMM)。但是,现有的加速器要么支持有限的N:M配置,要么需要针对不同的稀疏性模式进行硬件再生。这种限制阻碍了在最优稀疏模式下的有效加速,迫使次优N:M配置或硬件重新设计,并导致模型精度降低。为了解决这个问题,我们提出了FlexNM,一个完全灵活的N:M结构SpMM加速器。FlexNM采用统一的硬件架构,支持多种N:M值,可以在最佳N:M稀疏配置下直接加速工作负载。为了实现这种灵活性,FlexNM采用了一种新的非对称加法树(AAT)映射方案,该方案有效地支持不同的N值。它还结合了基于位图的压缩方案,以减少内存开销并增强N:M的灵活性。FPGA实验结果表明,FlexNM在密集收缩阵列基线上实现了高达15.94倍的加速,而相对于相同的基线,需要1.47倍的LUT和1.54倍的FF使用。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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